1. Field of the Invention
The present invention relates to a semiconductor storage device, such as a semiconductor storage device including a MIS transistor including a charge storage layer.
2. Description of the Related Art
Conventionally, NAND-type EEPROMs are widely used as nonvolatile semiconductor memories. A NAND-type EEPROM includes a memory cell array and a peripheral circuit disposed around the array. A structure of this type is disclosed in, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2002-324400.
In a conventional NAND-type EEPROM, the direction from the source to the drain in each memory cell is parallel to or perpendicular to the direction from the source to the drain or the direction from the drain to the source in each MIS transistor in the peripheral circuit. This arrangement is intended to facilitate placement of transistors and resist openings used in photolithography steps.
Further, conventionally, a NAND-type EEPROM is formed on the (001)-plane of a semiconductor substrate, wherein the direction from the source to the drain in each memory cell is parallel to the [110]-direction of the semiconductor substrate (crystal orientation). This is so, because silicon crystal mainly used for semiconductor substrates has a cleavage property in the [110]-direction. Accordingly, in the NAND-type EEPROM, the direction from the source to the drain or the direction from the drain to the source in each MIS transistor in the peripheral circuit is also parallel to the [110]-direction.
However, the conventional NAND-type EEPROM described above has a problem in that program disturbance is caused due to generation of hot carriers within memory cells. Further, carriers in each MIS transistor flow in the [110]-direction of the semiconductor substrate. Consequently, the performance of an n-type MIS transistor is larger than that of a p-type MIS transistor. This brings about a problem in that the performance difference between the n-type MIS transistor and the p-type MIS transistor becomes larger.